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slolson's avatar
slolson
Icon for New Contributor rankNew Contributor
1 year ago
Solved

Error: spi_0: Failed to find module spi_spi_0

I am trying to generate the SPI (4 Wire Serial) Intel FPGA IP core, but the platform designer fails to generate the HDL. It looks like it could be due to "Info: spi_0: Illegal division by zero at /to...
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  • ShengN_altera's avatar
    ShengN_altera
    1 year ago

    Hi,


    Please don't export the clock and reset ports then connect those ports to the clock source.


    Thanks,

    regards,

    Sheng


ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,


That SPI IP is always associated with other ip. So please generate it together with other IPs in .qsys system instead of standalone.


slolson's avatar
slolson
Icon for New Contributor rankNew Contributor
1 year ago

I see. To clarify, I was wondering why this IP requires a clock source, whereas others don't. What makes this one different? Thank you.