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slolson's avatar
slolson
Icon for New Contributor rankNew Contributor
8 months ago
Solved

Error: spi_0: Failed to find module spi_spi_0

I am trying to generate the SPI (4 Wire Serial) Intel FPGA IP core, but the platform designer fails to generate the HDL. It looks like it could be due to "Info: spi_0: Illegal division by zero at /to...
Hdl
Platform
  • ShengN_altera's avatar
    ShengN_altera
    8 months ago

    Hi,


    Please don't export the clock and reset ports then connect those ports to the clock source.


    Thanks,

    regards,

    Sheng


ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
8 months ago

Hi,


Please don't export the clock and reset ports then connect those ports to the clock source.


Thanks,

regards,

Sheng


slolson's avatar
slolson
Icon for New Contributor rankNew Contributor
8 months ago

That worked! Thank you. Why was the clock source needed in this case but not always using other IP cores in Platform Designer?