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slolson's avatar
slolson
Icon for New Contributor rankNew Contributor
1 year ago
Solved

Error: spi_0: Failed to find module spi_spi_0

I am trying to generate the SPI (4 Wire Serial) Intel FPGA IP core, but the platform designer fails to generate the HDL. It looks like it could be due to "Info: spi_0: Illegal division by zero at /to...
Hdl
Platform
  • ShengN_altera's avatar
    ShengN_altera
    1 year ago

    Hi,


    Please don't export the clock and reset ports then connect those ports to the clock source.


    Thanks,

    regards,

    Sheng


ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,


Could you double click the IP to see any error settings configuration?

If got error, it'll not be generated.


Thanks,

Regards,

Sheng


slolson's avatar
slolson
Icon for New Contributor rankNew Contributor
1 year ago

Yes, no errors after configuration before generating HDL.