Error (10644): Verilog HDL error at flexspi_dqs_phase_chain.v(81): this block requires a name

Hello,

Error (10644): Verilog HDL error at flexspi_dqs_phase_chain.v(81): this block requires a name

This not supported verilog coding style seems still not supported by quartus 21.1.0 (latest available version for the cyclone 5).

Will it be supported soon?

Otherwhise I have to go back to synplify,

I don't want to change many RTL code files anymore by adding name to please Quartus (like I did in a previous project).

Code example:

genvar j;
generate
for (j=0;j<DATA_LEARN_PHASE_NUM;j=j+1) begin
mux2_clock_wrapper u_mux2_dqs_phase (
.Z ( out[j] ),
.S0 ( i_ipt_global_scan_mode ),
.D0 ( phase[j] ),
.D1 ( i_test_clk_sfck )
)/* synthesis syn_preserve=1 */;
end
endgenerate