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AEsqu's avatar
AEsqu
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4 years ago

Error (10644): Verilog HDL error at flexspi_dqs_phase_chain.v(81): this block requires a name

Hello, Error (10644): Verilog HDL error at flexspi_dqs_phase_chain.v(81): this block requires a name This not supported verilog coding style seems still not supported by quartus 21.1.0 (latest ...
YEan's avatar
YEan
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4 years ago

Hi there,

Quartus Pro and Quartus standard use different front end code base. Unfortunately, we have no plan to change Quartus Standard front end currently.

Thanks,

Ean

AEsqu's avatar
AEsqu
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4 years ago

I will use Synplify for now then.

Please inform us when Quartus STD properly compiles the verilog.

Alex.

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    Hi @AEsqu

    The Quartus standard use a different synthesis engine or parser so I doubt that this will be supported in future.

    You may workaround this error by adding a line as below

    for (j=0;j<DATA_LEARN_PHASE_NUM;j=j+1)

    begin: a_name

    Best Regards,
    Richard Tan

    p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.

    • AEsqu's avatar
      AEsqu
      Icon for Contributor rankContributor
      4 years ago

      Hi Richard,

      I don't understand why the quartus pro edition does not support the Cyclone (V) FPGA's.

      That would solve this issue (we have pro licenses).

      Alex.

      • sstrell's avatar
        sstrell
        Icon for Super Contributor rankSuper Contributor
        4 years ago

        Cyclone V is only supported in Standard (and Lite which is free). If that's the device you're targeting, you should have a Standard license, not Pro. Pro only supports high end devices: Arria 10, Cyclone 10 GX, Stratix 10, and Agilex.