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AEsqu's avatar
AEsqu
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4 years ago

Error (10644): Verilog HDL error at flexspi_dqs_phase_chain.v(81): this block requires a name

Hello, Error (10644): Verilog HDL error at flexspi_dqs_phase_chain.v(81): this block requires a name This not supported verilog coding style seems still not supported by quartus 21.1.0 (latest ...
YEan's avatar
YEan
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4 years ago

I'm able to duplicate the error when I copied code to Quartus prime 21.1 std. I have no issue when using generate in Quartus Pro 21.4. I'll check again with the internal engineer and get back to you as soon as possible.

Thanks,

Ean