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AEsqu
Contributor
4 years agoError (10644): Verilog HDL error at flexspi_dqs_phase_chain.v(81): this block requires a name
Hello,
Error (10644): Verilog HDL error at flexspi_dqs_phase_chain.v(81): this block requires a name
This not supported verilog coding style seems still not supported by quartus 21.1.0 (latest ...
AEsqu
Contributor
4 years agoJust use generate without name.