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AEsqu's avatar
AEsqu
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4 years ago

Error (10644): Verilog HDL error at flexspi_dqs_phase_chain.v(81): this block requires a name

Hello, Error (10644): Verilog HDL error at flexspi_dqs_phase_chain.v(81): this block requires a name This not supported verilog coding style seems still not supported by quartus 21.1.0 (latest ...
AEsqu's avatar
AEsqu
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4 years ago

Hello,

The qar seems corrupted.

I use Quartus prime 21.1 std (latest supporting the Cyclone 5).

See the attached picture for the error.

YEan's avatar
YEan
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4 years ago

Hi there,

Quartus Pro and Quartus standard use different front end code base. Unfortunately, we have no plan to change Quartus Standard front end currently.

Thanks,

Ean