New ContributorEarly timing analysis + Intel's IP
Hello,
I updated Quartus Prime Pro to version 23.4, which gives me access to the Early Timing Analysis using RTL-on-SDC files.
The majorities of my clocks are defined by the sdc files automatically created by the Multi Channel DMA and PLL IPs.
When running the synthesis flow up to the Early Timing Analysis check, I see the PLL clock being sourced from the PLL IP files, but I don't see the PCIe application clock from the Multi Channel DMA files.
How can I add the PCIe clock to be used during Early Timing Analysis?
I tried to manually create the clock using the sdc command below
create_clock -name pcie_clk -period 2.000 -waveform {0 1} [get_pins {pcie_sys_inst|intel_pcie_ptile_mcdma_0|ast_hip|intel_pcie_ptile_ast_hip|inst|inst|maib_and_tile|hdpldadapt_rx_chnl_15|pld_pcs_rx_clk_out1_dcm}] -add
but it doesnt seem to work, quartus seems to ignore this line while loading the sdc file during synthesis.
Thanks for your help!
