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matferronato
New Contributor
New ContributorEarly timing analysis + Intel's IP
Hello, I updated Quartus Prime Pro to version 23.4, which gives me access to the Early Timing Analysis using RTL-on-SDC files. The majorities of my clocks are defined by the sdc files automatically...
matferronatoNew Contributor
New ContributorHi TingJiang, I see, know I understand your question better.
Yes, when I run a full compilation I see all the expected clocks both in the compilation reports and in the Timing Analyzer.
The problem only seems to appear in the dni flow, on the early timing analysis step.
