ContributorDual port RAM Cyclone 5
Hello,
I'm used to use this RTL code in Synplify to instantiate dual port ram for other FPGA's than the cyclone 5:
module dp_block
(
// memory port 1
p1_clk,
p1_addr,
p1_din,
p1_dout,
p1_we,
p1_re,
p1_ena,
// memory port 2
p2_clk,
p2_addr,
p2_din,
p2_dout,
p2_we,
p2_re,
p2_ena
)/*synthesis syn_ramstyle="no_rw_check"*/;
// memory parameter
parameter ADDR_BIT_WIDTH = 8;
parameter DATA_BIT_WIDTH = 16;
// memory port 1
input p1_clk;
input [ADDR_BIT_WIDTH-1:0] p1_addr;
input [DATA_BIT_WIDTH-1:0] p1_din;
input p1_we;
input p1_re;
input p1_ena;
output [DATA_BIT_WIDTH-1:0] p1_dout;
reg [DATA_BIT_WIDTH-1:0] p1_dout;
// memory port 2
input p2_clk;
input [ADDR_BIT_WIDTH-1:0] p2_addr;
input [DATA_BIT_WIDTH-1:0] p2_din;
input p2_we;
input p2_re;
input p2_ena;
output [DATA_BIT_WIDTH-1:0] p2_dout;
reg [DATA_BIT_WIDTH-1:0] p2_dout;
// memory
reg [DATA_BIT_WIDTH-1:0] mem [0:(2**ADDR_BIT_WIDTH)-1];
always @(posedge p1_clk) begin
if (p1_ena)
begin
if (p1_we)
mem[p1_addr] <= p1_din;
p1_dout <= mem[p1_addr];
end
end
always @(posedge p2_clk) begin
if (p2_ena)
begin
if (p2_we)
mem[p2_addr] <= p2_din;
p2_dout <= mem[p2_addr];
end
end
endmodule
This is not working for the cyclone 5 apparently (write conflict),
Synplify team told me that Cyclone 5 M10K block only supports new data instead of old data at the read port.
In the Intel coding style reference for the Cyclone 5 document,
I do not see the verilog code example for dual port ram with 2 clocks, like above.
What would be the RTL code to make it work with the cyclone 5?
I have attached a ip configuration picture that would match the RTL code (unfortunately I couldn't find a way in Quartus 21.1 to create verilog/vhdl code for the dual port,
only netlist generation, which is not for me as I use it for different ram sizes and want to keep it generic with only one RTL code for Synplify.
Kind Regards,
Alexandre.
