Dual port RAM Cyclone 5

In the Quartus text editor true dual port RAM (dual clock) template (Text Editor Edit menu -> Insert Template), it's a bit different from what you have. New data would imply that on write, you should have, along with writing to the RAM:

p1_dout <= p1_din; //similar for p2

You're also missing in your if statements an else check for if p1_we (or p2_we) are low:

p1_dout <= mem[p1_addr]; //again similar for p2

I'm also not sure if there are separate RAM enable signals like what you have (p1_ena and p2_ena). They are not in the template.

Any of these could affect how the RAM gets inferred and whether extra external logic gets added to match your behavioral description.