Dual port RAM Cyclone 5

Synopsys provided me an updated m_altera file for Synplify, that supports the enable in the dual port ram RTL code,

(that was supported for the xilinx mapper).

The code below is now compiling well for the cyclone V.

module dp_block
#(parameter DATA_BIT_WIDTH=16, parameter ADDR_BIT_WIDTH=8)
(
  input [(DATA_BIT_WIDTH-1):0] p1_din, p2_din,
  input [(ADDR_BIT_WIDTH-1):0] p1_addr, p2_addr,
  input p1_we, p2_we, p1_clk, p1_re, p1_ena, p2_clk, p2_re, p2_ena,
  output reg [(DATA_BIT_WIDTH-1):0] p1_dout, p2_dout
)/*synthesis syn_ramstyle="no_rw_check"*/;

  // Declare the RAM variable
  reg [DATA_BIT_WIDTH-1:0] ram[2**ADDR_BIT_WIDTH-1:0];

  always @ (posedge p1_clk)
    begin
      if (p1_ena)
        begin
          if (p1_we) 
            begin
              ram[p1_addr] <= p1_din;
              p1_dout <= p1_din;
            end
          else 
            begin
              p1_dout <= ram[p1_addr];
            end 
        end
    end

  always @ (posedge p2_clk)
    begin
      if (p2_ena)
        begin 
          if (p2_we) 
            begin
              ram[p2_addr] <= p2_din;
              p2_dout <= p2_din;
            end
          else 
            begin
              p2_dout <= ram[p2_addr];
            end 
        end
    end

endmodule