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AEsqu's avatar
AEsqu
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4 years ago

Dual port RAM Cyclone 5

Hello, I'm used to use this RTL code in Synplify to instantiate dual port ram for other FPGA's than the cyclone 5: module dp_block ( // memory port 1 p1_clk, p1_addr, p1_din, p1_dout, p1_w...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
4 years ago

Again, I don't think p1_ena or p2_ena are valid signals for the RAM. They're still in your code.

AEsqu's avatar
AEsqu
Icon for Contributor rankContributor
4 years ago

Thank You, Synplify is indeed able to map the RAM in the cyclone 5 when the enables are removed.

  • ShengN_altera's avatar
    ShengN_altera
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    Hi,

    Looks like the issue addressed had been resolved.
    I'll now transition this thread to community support.
    If you have a new question, feel free to open a new thread to get the support from Intel experts.

    Thank you.

    Best regards,
    Sheng
    p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.