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AEsqu's avatar
AEsqu
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4 years ago

Dual port RAM Cyclone 5

Hello, I'm used to use this RTL code in Synplify to instantiate dual port ram for other FPGA's than the cyclone 5: module dp_block ( // memory port 1 p1_clk, p1_addr, p1_din, p1_dout, p1_w...
AEsqu's avatar
AEsqu
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4 years ago

Synplify still errors out when using the RAM close to the Quartus template (on a ram bigger than 32 bits, using 7 8 bits blocks of dp_block):

@E:MF212 : dp_block.v(30) | Cannot map ....mem.I_dp_block_6.ram_1[7:0] due to multiple write clocks.

Looks like a synplify bug.

I have attached the file where both your remarks are in.