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HypeInst's avatar
HypeInst
Icon for New Contributor rankNew Contributor
5 years ago

Difference in SystemVerilog-2005 HDL simulation behavior between Quartus Prime and ModelSim

I am testing a SystemVerilog module by comparing the simulation results between the two following cases:

Case 1: Compiling in Quartus Prime and then simulating in ModelSim-Intel
Case 2: Compiling in ModelSim-Intel and then simulating in ModelSim-Intel

The following is the SystemVerilog code:

module always_ff_process();

reg [7:0] sum,a,b;
reg       parity;
logic     clk = 0;
reg       rst = 0;

initial begin
  $monitor ("@%g clk = %b rst = %b a = %h b = %h sum = %h parity = %b", 
  $time, clk, rst, a, b, sum, parity);
  #1 rst = 1;
  #5 rst = 0;
  #2 a = 1;
  #2 b = 1;
  #2 a = 10;
  #2 $finish;
end

always #1 clk ++;

// use of iff makes sure that block does not get
// triggered due to posedge of clk when rst == 1
always_ff @(posedge clk iff rst == 0 or posedge rst)
begin : ADDER
  if (rst) begin
    sum    <= 0;
    parity <= 0;
    $display ("Reset is asserted BLOCK 1");
  end else begin
    sum    <= b + a;
    parity <= ^(b + a);
  end
end

// To show how iff affected in earlier code
always_ff @(posedge clk or posedge rst)
begin
  if (rst) begin
    $display ("Reset is asserted BLOCK 2");
  end 
end

endmodule

I obtain the following simulation results for Case 1:

@0 clk = 0 rst = 0 a = xx b = xx sum = xx parity = x
Reset is asserted BLOCK 1
Reset is asserted BLOCK 2
@1 clk = 1 rst = 1 a = xx b = xx sum = 00 parity = 0
@2 clk = 0 rst = 1 a = xx b = xx sum = 00 parity = 0
Reset is asserted BLOCK 1
Reset is asserted BLOCK 2
@3 clk = 1 rst = 1 a = xx b = xx sum = 00 parity = 0
@4 clk = 0 rst = 1 a = xx b = xx sum = 00 parity = 0
Reset is asserted BLOCK 1
Reset is asserted BLOCK 2
@5 clk = 1 rst = 1 a = xx b = xx sum = 00 parity = 0
@6 clk = 0 rst = 0 a = xx b = xx sum = 00 parity = 0
@7 clk = 1 rst = 0 a = xx b = xx sum = xx parity = x
@8 clk = 0 rst = 0 a = 01 b = xx sum = xx parity = x
@9 clk = 1 rst = 0 a = 01 b = xx sum = xx parity = x
@10 clk = 0 rst = 0 a = 01 b = 01 sum = xx parity = x
@11 clk = 1 rst = 0 a = 01 b = 01 sum = 02 parity = 1
@12 clk = 0 rst = 0 a = 0a b = 01 sum = 02 parity = 1
@13 clk = 1 rst = 0 a = 0a b = 01 sum = 0b parity = 1

I obtain the following simulation results for Case 2:

@0 clk = 0 rst = 0 a = xx b = xx sum = xx parity = x
Reset is asserted BLOCK 2
Reset is asserted BLOCK 1
@1 clk = 1 rst = 1 a = xx b = xx sum = 00 parity = 0
@2 clk = 0 rst = 1 a = xx b = xx sum = 00 parity = 0
Reset is asserted BLOCK 2
@3 clk = 1 rst = 1 a = xx b = xx sum = 00 parity = 0
@4 clk = 0 rst = 1 a = xx b = xx sum = 00 parity = 0
Reset is asserted BLOCK 2
@5 clk = 1 rst = 1 a = xx b = xx sum = 00 parity = 0
@6 clk = 0 rst = 0 a = xx b = xx sum = 00 parity = 0
@7 clk = 1 rst = 0 a = xx b = xx sum = xx parity = x
@8 clk = 0 rst = 0 a = 01 b = xx sum = xx parity = x
@9 clk = 1 rst = 0 a = 01 b = xx sum = xx parity = x
@10 clk = 0 rst = 0 a = 01 b = 01 sum = xx parity = x
@11 clk = 1 rst = 0 a = 01 b = 01 sum = 02 parity = 1
@12 clk = 0 rst = 0 a = 0a b = 01 sum = 02 parity = 1
@13 clk = 1 rst = 0 a = 0a b = 01 sum = 0b parity = 1

Both Quartus Prime and ModelSim-Intel support SystemVerilog-2005. However, Quartus Prime's compiler doesn't appear to support clock-edge gating (the "iff" conditional) even though it's legal SystemVerilog-2005. I have set the settings of both compilers to SystemVerilog and I cannot find any other applicable settings.

Please advise. Thank you!

11 Replies

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    May I know which Intel Quartus Prime edition (Pro/Std) and version you are using?


    Thanks

    Best regards,

    KhaiY


    • HypeInst's avatar
      HypeInst
      Icon for New Contributor rankNew Contributor
      5 years ago

      I am using Quartus Prime Lite Version 20.1 and ModelSim-Intel Version 2020.1.

    • HypeInst's avatar
      HypeInst
      Icon for New Contributor rankNew Contributor
      5 years ago

      Intel Quartus Prime Lite supposedly supports SystemVerilog-2005, and the code that I am simulating is SystemVerilog-2005 compliant.

      Actually, Quartus Prime Lite does not compile the following block:

      always_ff @(posedge clk iff rst == 0 or posedge rst) begin
	if (rst) begin
		sum    <= 0;
		parity <= 0;
		$display ("Reset is asserted BLOCK 1");
	end
	else begin
		sum    <= b + a;
		parity <= ^(b + a);
	end
end

      I receive the following error message:

      Error (10170): Verilog HDL syntax error near text: "iff"; expecting ")".

      However, the "iff" conditional in the always@ sensitivities list is SystemVerilog-2005 compliant.

      Please advise.

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,

    I see the same message when I compile the design in the Lite edition. This is due to the limited language support in the Lite edition as mentioned in https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/po/ss-quartus-comparison.pdf

    I tried to compile the design in the Pro edition, the software did not issue this message during compilation. You may consider to upgrade the software to Pro edition

    Thanks

    Best regards,

    KhaiY

    • HypeInst's avatar
      HypeInst
      Icon for New Contributor rankNew Contributor
      5 years ago

      Intel claims that Quartus Prime Lite supports SystemVerilog-2005. Quartus Prime Pro supports SystemVerilog-2005, SystemVerilog-2009, and SystemVerilog-2012. This information is contained in the "Design Compilation" User Guides for the softwares.

      The "iff" gated clock feature of the always@ block is supported by SystemVerilog-2005.

      Quartus Prime Pro doesn't support the FPGA device (Cyclone V) that I am targeting, so an upgrade to Quartus Prime Pro isn't a feasible solution.

  • antoniol's avatar
    antoniol
    Icon for New Contributor rankNew Contributor
    5 years ago

    Verilog HDL

    -SystemVerilog

    • For RTL simulation in Verilog HDL or SystemVerilog, compile your design files in your simulator. You must also compile simulation models from the Intel FPGA simulation libraries and simulation models for the IP cores in your design. Use the Simulation Library Compiler to compile simulation models.
    • For gate-level simulation, the EDA Netlist Writer generates a synthesized design netlist Verilog Output File (.vo). Compile the .vo in your simulator.\
    Prime Standard Edition
    • The NativeLink feature integrates your EDA simulator with the Intel® Quartus® Prime Standard Edition software by automating the following:
      • Generation of simulator-specific files and simulation scripts.
  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,

    We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


    Best regards,

    KhaiY