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HypeInst's avatar
HypeInst
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5 years ago

Difference in SystemVerilog-2005 HDL simulation behavior between Quartus Prime and ModelSim

I am testing a SystemVerilog module by comparing the simulation results between the two following cases: Case 1: Compiling in Quartus Prime and then simulating in ModelSim-Intel Case 2: Compiling ...
antoniol's avatar
antoniol
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5 years ago

Verilog HDL

-SystemVerilog

  • For RTL simulation in Verilog HDL or SystemVerilog, compile your design files in your simulator. You must also compile simulation models from the Intel FPGA simulation libraries and simulation models for the IP cores in your design. Use the Simulation Library Compiler to compile simulation models.
  • For gate-level simulation, the EDA Netlist Writer generates a synthesized design netlist Verilog Output File (.vo). Compile the .vo in your simulator.\
Prime Standard Edition
  • The NativeLink feature integrates your EDA simulator with the Intel® Quartus® Prime Standard Edition software by automating the following:
    • Generation of simulator-specific files and simulation scripts.