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Re: IP_XACT_REGISTER_MAP for PCIE And DDR controller
Hi Sengkok, thanks for your fast reply. What about IP_XACT_REGISTER_MAP for DDR controller? I was created example design of PCIe_Multi channel DMA Express and DDR controller. In that pcie_ed.ipxact and ed_sim_emif.ipxact file was generated. here it was not mentioning the Registers of PCIe Multi channel DMA and DDR controllers. It shows only bus interface and port map of that if possible please arrange webx meeting and this is my highest priority <?xml version="1.0" encoding="UTF-8" standalone="yes"?> <ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"> <ipxact:vendor>Altera Corporation</ipxact:vendor> <ipxact:library>pcie_ed</ipxact:library> <ipxact:name>pcie_ed</ipxact:name> <ipxact:version>1.0</ipxact:version> <ipxact:busInterfaces> <ipxact:busInterface> <ipxact:name>refclk</ipxact:name> <ipxact:busType vendor="altera" library="altera" name="clock" version="20.2"/> <ipxact:abstractionTypes> <ipxact:abstractionType> <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="20.2"/> <ipxact:portMaps> <ipxact:portMap> <ipxact:logicalPort> <ipxact:name>clk</ipxact:name> </ipxact:logicalPort> <ipxact:physicalPort> <ipxact:name>refclk_clk</ipxact:name> </ipxact:physicalPort> </ipxact:portMap> </ipxact:portMaps> </ipxact:abstractionType> </ipxact:abstractionTypes> <ipxact:slave/> <ipxact:parameters> <ipxact:parameter parameterId="clockRate" type="longint"> <ipxact:name>clockRate</ipxact:name> <ipxact:displayName>Clock rate</ipxact:displayName> <ipxact:value>100000000</ipxact:value> </ipxact:parameter> <ipxact:parameter parameterId="externallyDriven" type="bit"> <ipxact:name>externallyDriven</ipxact:name> <ipxact:displayName>Externally driven</ipxact:displayName> <ipxact:value>false</ipxact:value> </ipxact:parameter> <ipxact:parameter parameterId="ptfSchematicName" type="string"> <ipxact:name>ptfSchematicName</ipxact:name> <ipxact:displayName>PTF schematic name</ipxact:displayName> <ipxact:value></ipxact:value> </ipxact:parameter> </ipxact:parameters> </ipxact:busInterface> <ipxact:busInterface> <ipxact:name>pcie_rstn</ipxact:name> Thanks in Advance Indirapriya3.8KViews0likes0CommentsPCIE Gen4x16 example design
Hi, The downstream component is backpressing by deasserting ready, but upstream component cant be backpressed. can you please clarify the below questions: 1.Testcase flow of PCIe BFM. How to execute different tests?(Which Modules need to look ) 2.Need procedure for Testing Memory write and Read (32- and 64-bit address) TLP's. 3.How to configure the Descriptor for DMA modes(Write and Read) in PCIE RC BFM? Thanks in Advance IndirapriyaSolved1.5KViews0likes1CommentNIOS II embedded processor vs Hard processor system on Stratix 10 dx device
Hi, what is the difference between NIOS II embedded processor vs Hard processor system on Stratix 10 dx device? which processor is same as microblaze in xilinx? i need a reference design for bothSolved894Views0likes1CommentNot able modify testbench BFM Intel P tile PCIE avmm example design on Stratix 10DX device
Hi all, I ran PCIE Gen4x16 ptile avmm example design while running it and I got the VCS report which i attach it. In that report, I analyze the report and i noticed that "upstream component can't be backpressed". I attach the snapshot of that can you please clarify the below questions: 1.Testcase flow of PCIe BFM. How to execute different tests?(Which Modules need to look ) 2.Need procedure for Testing Memory write and Read (32- and 64-bit address) TLP's. 3.How to configure the Descriptor for DMA modes(Write and Read) in PCIE RC BFM? Thanks in Advance Indirapriya811Views0likes1Comment