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HypeInst's avatar
HypeInst
Icon for New Contributor rankNew Contributor
5 years ago

Difference in SystemVerilog-2005 HDL simulation behavior between Quartus Prime and ModelSim

I am testing a SystemVerilog module by comparing the simulation results between the two following cases: Case 1: Compiling in Quartus Prime and then simulating in ModelSim-Intel Case 2: Compiling ...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

I see the same message when I compile the design in the Lite edition. This is due to the limited language support in the Lite edition as mentioned in https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/po/ss-quartus-comparison.pdf

I tried to compile the design in the Pro edition, the software did not issue this message during compilation. You may consider to upgrade the software to Pro edition

Thanks

Best regards,

KhaiY

  • HypeInst's avatar
    HypeInst
    Icon for New Contributor rankNew Contributor
    5 years ago

    Intel claims that Quartus Prime Lite supports SystemVerilog-2005. Quartus Prime Pro supports SystemVerilog-2005, SystemVerilog-2009, and SystemVerilog-2012. This information is contained in the "Design Compilation" User Guides for the softwares.

    The "iff" gated clock feature of the always@ block is supported by SystemVerilog-2005.

    Quartus Prime Pro doesn't support the FPGA device (Cyclone V) that I am targeting, so an upgrade to Quartus Prime Pro isn't a feasible solution.