Forum Discussion

HypeInst's avatar
HypeInst
Icon for New Contributor rankNew Contributor
5 years ago

Difference in SystemVerilog-2005 HDL simulation behavior between Quartus Prime and ModelSim

I am testing a SystemVerilog module by comparing the simulation results between the two following cases: Case 1: Compiling in Quartus Prime and then simulating in ModelSim-Intel Case 2: Compiling ...
HypeInst's avatar
HypeInst
Icon for New Contributor rankNew Contributor
5 years ago

Intel Quartus Prime Lite supposedly supports SystemVerilog-2005, and the code that I am simulating is SystemVerilog-2005 compliant.

Actually, Quartus Prime Lite does not compile the following block:

always_ff @(posedge clk iff rst == 0 or posedge rst) begin
	if (rst) begin
		sum    <= 0;
		parity <= 0;
		$display ("Reset is asserted BLOCK 1");
	end
	else begin
		sum    <= b + a;
		parity <= ^(b + a);
	end
end

I receive the following error message:

Error (10170): Verilog HDL syntax error near text: "iff"; expecting ")".

However, the "iff" conditional in the always@ sensitivities list is SystemVerilog-2005 compliant.

Please advise.