Altera_Forum
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17 years agoDetermine address width in Verilog HDL with $clog2
Dear all,
Does anybody know how to use the Verilog HDL $clog2 math function with the Quartus II software? I am trying to use the clog2 (=ceil(log2(x))) function to calculate the address width needed for a RAM block with x number of words, since I think it's a bit silly to have to input two different parameter values in a parametrized module when the parameters are equivalent. However, when I try to compile my design in Quartus, I get the follwing error: Error (10174): Verilog HDL Unsupported Feature error at VPP.v(82): system function "$clog2" is not supported for synthesis Any idea what I did wrong? Thanks in advance. Faruk