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Altera_Forum
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17 years ago

Determine address width in Verilog HDL with $clog2

Dear all, Does anybody know how to use the Verilog HDL $clog2 math function with the Quartus II software? I am trying to use the clog2 (=ceil(log2(x))) function to calculate the address...
Altera_Forum's avatar
Altera_Forum
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16 years ago

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Although for altera it can be outside the module, but this is not standard, and can cause problems with some simulators.

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Quartus II allows global functions if you are compiling with SystemVerilog extensions. Otherwise, you should get an error.