Determine address width in Verilog HDL with $clog2

Hello Stefaan,

Thanks very much, I was able to use your code example to calculate the address widths.

By the way, the IEEE Verilog standard mentions that the constant function must be defined locally within the module. This would mean that every time I would like to use the CLogB2 function I have to define the function within that module (locally). I guess that one way to solve this is to define useful functions in a header file and include the header when necessary:

main.v

module main(..)
 
`include "MathFun.vh"
parameter address_width=CLogB2(num_words);
 
endmodule

MathFun.vh

//ceil of the log base 2
function integer CLogB2;
    input  Depth;
    integer i;
    begin
         i = Depth;        
        for(CLogB2 = 0; i > 0; CLogB2 = CLogB2 + 1)
            i = i >> 1;
    end
endfunction

Another way would be to try convince Altera that a function such as log2 is actually very useful in the real world ...(and that they should listen to the IEEE guys who have $clog2 as part of the standard :) )

Faruk