Determine address width in Verilog HDL with $clog2

In quartus, you have to use the so called "constant functions". This is a function that operates only on cosntants, and so can be used during the first steps of the synthesis:

module pulse(input Clk, input Reset, output Pulse);
parameter COUNTS = 33;
reg  count;
assign Pulse = count == 0;
always @(posedge Clk or posedge Reset)
	if (Reset)
		count <= 0;
	else
		count <= count + 1;
//ceil of the log base 2
function integer CLogB2;
	input  Depth;
	integer i;
	begin
	 	i = Depth;		
		for(CLogB2 = 0; i > 0; CLogB2 = CLogB2 + 1)
			i = i >> 1;
	end
endfunction
endmodule