Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Determine address width in Verilog HDL with $clog2

Dear all, Does anybody know how to use the Verilog HDL $clog2 math function with the Quartus II software? I am trying to use the clog2 (=ceil(log2(x))) function to calculate the address...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Put the function into a package, and then call it from anywhere. I do it in package utils and then call it with utils::clog2()

Simple and organized, and there is no need to add an include.