Determine address width in Verilog HDL with $clog2

Faruk,

I put the function in the module everytime (I copy it in at the bottom every time). It's not that much work, and the functionality stays like you wrote it. For example if for some reason the function has to change, it can affect all your files that include MathFun.vh. I know in this case it will be unlikely that the CLogB2 function will change...

Although for altera it can be outside the module, but this is not standard, and can cause problems with some simulators.

Stefaan