Cyclone 10GX Transceiver TX and RX independent

i used the document from the link below and created the example design

https://www.intel.com/content/www/us/en/programmable/documentation/dbf1520991817584.html

The example used transceiver in duplex mode but i wanted to try tx and rx in simplex mode.i created a tx and rx ip separately using the same ip parameters and used it in the altera_eth_wrapper. I am trying to understand the working of the transceiver .

Yes i am using cyclone 10gx dev kit(10CX220YF780E5G) .The example design passed the hardware test without any modifications .

hi,

thanks for the kdb article ,I am currently trying to understand the working of the Transceiver and wanted to know how it would work if set in simplex mode. In the altera_eth_base_r_wrapper.v file i have set the tx and rx pins as

.reconfig_clk (csr_clk),
.reconfig_reset (~csr_rst_n),
.reconfig_write (phy_csr_write),
.reconfig_read (phy_csr_read),
.reconfig_address (phy_csr_address),
.reconfig_writedata (phy_csr_writedata),

When i tried this the the same issue occurs .Is this the right way to do it or should i change it in the platform designer?

Hi ,

In the qsys file ,i have added the TX and RX ip files and an Avalon pipeline bridge ip. In the platform designer ,gave the same wire level expressions as in the KDB article .Now another issue occurs

Error(12829): Failed to merge HSSI Avalon Memory-Mapped interface instances "dut_inst|CHANNEL[0].wrapper_inst|u0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst" and "dut_inst|CHANNEL[0].wrapper_inst|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst" into single Avalon Memory-Mapped Interface.
Error(12829): Failed to merge HSSI Avalon Memory-Mapped interface instances "dut_inst|CHANNEL[1].wrapper_inst|u0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst" and "dut_inst|CHANNEL[1].wrapper_inst|u1|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst" into single Avalon Memory-Mapped Interface.

What is the workaround for this issue??

Hi,

I am using 20.2 version Quartus Pro edition .

Hi Deshi, i worked with Visshnu on this subject for his internship, and he is now proceeding to his masters. Unfortunately, we didn't ,manage to map your design including our PHY design, to the cyclone.

The simulation works though, with the xcvr_x1_plb_s0 (Avalon-MM interface, readdata, writedata etc...) signals unconnected. I don't understand what the purpose of those signals are: The tx_parallel [63:0] signal carries the to-be-send signal, the tx_tx_serial signal carries the serial output, whereas rx_rx_serial receives the incoming signal, and the rx_rx_parallel[63:0] carries the received parallel data...For what do you then need this Avalon-MM interface?

Also, i am not really sure what we mean with simplex. My interpretation is: There is a channel[0], on the end of which there is a trcvr[0] with a tx channel. That channel is connected via the 10Gbps cable to the rx-channel of the trcvr[1] in channel[1]. Simplex as: there is only one channel, carrying traffic in one direction. Of course not very useful in normal datacommuncation, but more simple, and using less LU's.

A duplex system would then be:

A: there is a channel[0], with a tx_trcvr[0], connected via the 10gbps cable to rx_trcvr[1] in channel[1], AND a channel[1] with tx_trcvr[1], connected via the same cable, but different pair, to the rx_trcvr[0], to channel[0],

OR:

B: there is a channel[0], with a tx_trcvr[0], connected via the FMC card to rx_trcvr[0] in channel[0]

Please advise,

regards, Pieter