Cyclone 10GX Transceiver TX and RX independent

Hi Deshi, i worked with Visshnu on this subject for his internship, and he is now proceeding to his masters. Unfortunately, we didn't ,manage to map your design including our PHY design, to the cyclone.

The simulation works though, with the xcvr_x1_plb_s0 (Avalon-MM interface, readdata, writedata etc...) signals unconnected. I don't understand what the purpose of those signals are: The tx_parallel [63:0] signal carries the to-be-send signal, the tx_tx_serial signal carries the serial output, whereas rx_rx_serial receives the incoming signal, and the rx_rx_parallel[63:0] carries the received parallel data...For what do you then need this Avalon-MM interface?

Also, i am not really sure what we mean with simplex. My interpretation is: There is a channel[0], on the end of which there is a trcvr[0] with a tx channel. That channel is connected via the 10Gbps cable to the rx-channel of the trcvr[1] in channel[1]. Simplex as: there is only one channel, carrying traffic in one direction. Of course not very useful in normal datacommuncation, but more simple, and using less LU's.

A duplex system would then be:

A: there is a channel[0], with a tx_trcvr[0], connected via the 10gbps cable to rx_trcvr[1] in channel[1], AND a channel[1] with tx_trcvr[1], connected via the same cable, but different pair, to the rx_trcvr[0], to channel[0],

OR:

B: there is a channel[0], with a tx_trcvr[0], connected via the FMC card to rx_trcvr[0] in channel[0]

Please advise,

regards, Pieter