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Honored Contributor
Honored Contributorcreate generated clocks
In my system, there are a few clocks. I attach its extraction below, where clk1(50MHz) and clk0(100MHz) are irrelevant. It makes defining synced_clk1 difficult.
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7 Replies
Altera_ForumYou don't clarify the purpose of a derived clock in your case. But surely signals from clock domains clk0 and clk1 will cause timing issues when processing them in the syn_clk1 domain.
- Altera_Forum
Thanks, FvM.
I attach a simplied schematic to give a brief idea of how the clocks are used. - Altera_Forum
Which problems do you observe?
- Altera_Forum
setup/hold, max freq and general timing analysis.
- Altera_Forum
Assuming clko and clk1 as PLL generated clocks, I don't see particular timiming issues, except for the timing requirements for the unamed input in your schematic. I still don't understand the purpose of creating a ripple clock, however.
- Altera_Forum
clk0 can be one output of PLL generated clocks but clk1 is an external input. Yes, you are right. The timing requirements for the unamed input have to be analysed. Maybe this schematic does not describe what the actual design does. If I said that clk1 was an external clock and clk1 was of any frequency upto 50MHz, it would have been clearer. The issue is how to define synced_clk. Many thanks.
- Altera_Forum
If clk1 is an unrelated external clock, setup and hold timing can't be guaranteed for the first FF. Metastable FF states must be expected with a certain likelihood. Altera design recommendations suggest a double FF sync unit in this situation.
Also if clk1 is unrelated, you should be able to find a full synchronous construct instead of the present ripple clock design.
