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Honored Contributor
Honored Contributorcreate generated clocks
In my system, there are a few clocks. I attach its extraction below, where clk1(50MHz) and clk0(100MHz) are irrelevant. It makes defining synced_clk1 difficult.
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Altera_ForumHonored Contributor
Honored ContributorYou don't clarify the purpose of a derived clock in your case. But surely signals from clock domains clk0 and clk1 will cause timing issues when processing them in the syn_clk1 domain.
