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Altera_Forum's avatar
Altera_Forum
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16 years ago

create generated clocks

In my system, there are a few clocks. I attach its extraction below, where clk1(50MHz) and clk0(100MHz) are irrelevant. It makes defining synced_clk1 difficult.
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

clk0 can be one output of PLL generated clocks but clk1 is an external input. Yes, you are right. The timing requirements for the unamed input have to be analysed. Maybe this schematic does not describe what the actual design does. If I said that clk1 was an external clock and clk1 was of any frequency upto 50MHz, it would have been clearer. The issue is how to define synced_clk. Many thanks.