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Altera_Forum's avatar
Altera_Forum
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16 years ago

create generated clocks

In my system, there are a few clocks. I attach its extraction below, where clk1(50MHz) and clk0(100MHz) are irrelevant. It makes defining synced_clk1 difficult.
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

If clk1 is an unrelated external clock, setup and hold timing can't be guaranteed for the first FF. Metastable FF states must be expected with a certain likelihood. Altera design recommendations suggest a double FF sync unit in this situation.

Also if clk1 is unrelated, you should be able to find a full synchronous construct instead of the present ripple clock design.