Altera_Forum
Honored Contributor
Honored Contributorcreate generated clocks
In my system, there are a few clocks. I attach its extraction below, where clk1(50MHz) and clk0(100MHz) are irrelevant. It makes defining synced_clk1 difficult.
Forum Discussion
Altera_ForumHonored Contributor
Honored ContributorAssuming clko and clk1 as PLL generated clocks, I don't see particular timiming issues, except for the timing requirements for the unamed input in your schematic. I still don't understand the purpose of creating a ripple clock, however.
