Altera_Forum
Honored Contributor
16 years agocreate generated clocks
In my system, there are a few clocks. I attach its extraction below, where clk1(50MHz) and clk0(100MHz) are irrelevant. It makes defining synced_clk1 difficult.
Thanks, FvM.
I attach a simplied schematic to give a brief idea of how the clocks are used.