Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Counter between a data range(VHDL)

Hi, everyone.

This is the Counter I design, lines below:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity load_counter is

port( clk:in std_logic;

en:in std_logic;

data_out: out std_logic_vector(11 downto 0));

end entity;

architecture one of load_counter is

begin

process(clk,en)

variable temp:std_logic_vector(11 downto 0):="101100110110";

constant a1:std_logic_vector(11 downto 0):="010011001110";

begin

if en='1' then

if clk'event and clk='1' then

temp:=temp-1;

elsif temp=a1 then

temp:="010011001110";

end if;

end if;

data_out<=temp;

end process;

end one;

The error messages are:

Error (10818): Can't infer register for "temp[0]" at load_counter.vhd(18) because it does not hold its value outside the clock edge

Error (10818): Can't infer register for "temp[1]" at load_counter.vhd(18) because it does not hold its value outside the clock edge

Error (10818): Can't infer register for "temp[2]" at load_counter.vhd(18) because it does not hold its value outside the clock edge

Error (10818): Can't infer register for "temp[3]" at load_counter.vhd(18) because it does not hold its value outside the clock edge

Error (10818): Can't infer register for "temp[4]" at load_counter.vhd(18) because it does not hold its value outside the clock edge

Error (10818): Can't infer register for "temp[5]" at load_counter.vhd(18) because it does not hold its value outside the clock edge

Error (10818): Can't infer register for "temp[6]" at load_counter.vhd(18) because it does not hold its value outside the clock edge

Error (10818): Can't infer register for "temp[7]" at load_counter.vhd(18) because it does not hold its value outside the clock edge

Error (10818): Can't infer register for "temp[8]" at load_counter.vhd(18) because it does not hold its value outside the clock edge

Error (10818): Can't infer register for "temp[9]" at load_counter.vhd(18) because it does not hold its value outside the clock edge

Error (10818): Can't infer register for "temp[10]" at load_counter.vhd(18) because it does not hold its value outside the clock edge

Error (10818): Can't infer register for "temp[11]" at load_counter.vhd(18) because it does not hold its value outside the clock edge

Error (10822): HDL error at load_counter.vhd(18): couldn't implement registers for assignments on this clock edge

I mean to make it count between "010011001110" and "101100110110", but it doesn't work as I plan to.

I will appreciate it if anyone can give some help.

Thanks.

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    I have solved the problerm.

    The vhdl lines should be these.

    architecture one of load_counter is

    begin

    process(clk,en)

    variable temp:std_logic_vector(11 downto 0):="101100110110";

    constant a1:std_logic_vector(11 downto 0):="010011001110";

    begin

    if en='1' then

    if clk'event and clk='1' then

    if temp>a1 then

    temp:=temp-1;

    elsif temp=a1 then

    temp:="101100110110";

    end if;

    end if;

    end if;

    data_out<=temp;

    end process;

    end one;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    hi, i am experiencing a simillar problem with all the error messages are the bottm, i do not see how this code solves the problem, could you offer me some guidance please,

    regards,

    Zadok
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Simply, the counter reload must be done within in the clock edge sensitive block. otherwise the construct isn't synthesizable.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    i sorted that out by adding a counter to my statements but i got 700 warnings of the kind below when i compiled my schematic.

    Warning: No clock transition on "db2_rom4:inst30|r_data[1]" register due to stuck clock or clock enable

    Warning: Reduced register "db2_rom4:inst30|r_data[1]" with stuck clock port to stuck value GND

    --------------------

    most of the code in my blocks looks like this

    entity db2_rom1 is

    port(r_clk : in std_logic;--clock input at the user data frequency

    r_data : out std_logic_vector (9 downto 0)--wavelet data vector representing a portion of the wavelet

    );

    end db2_rom1;

    architecture daze of db2_rom1 is

    type mem is array (0 TO 9) of std_logic_vector (9 downto 0);

    constant rom : mem :=(

    0 => "0000000100",

    1 => "0000000111",

    2 => "1111101011",

    3 => "0000011100",

    4 => "1110110100",

    5 => "1111101011",

    6 => "0011000011",

    7 => "1110110100",

    8 => "1110011000",

    9 => "0000111011"

    );

    begin

    process(r_clk)

    variable count : integer :=0;--defining a counter

    begin

    if rising_edge(r_clk) then

    r_data<=rom(count);

    count:=count+1;

    if count=10 then --check whether the ROM addresses have been exceeded

    count:=0;

    end if;

    end if;

    end process;

    end daze;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    With Quartus 5.1 , no warnings and errors.

    What analysis and synthesis soft do you use?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    It works for me in Modelsim. I would guess that the clock is the problem

    --- Quote Start ---

    Warning: No clock transition on "db2_rom4:inst30|r_data[1]" register due to stuck clock or clock enable

    Warning: Reduced register "db2_rom4:inst30|r_data[1]" with stuck clock port to stuck value GND

    --- Quote End ---

    To me this warning says that quartus knows that there isn't a clock signal going into the block. The reason could be that there is an enable signal that is always held to zero or that you've connected the wrong clock signal to the block or something else of that kind. I would focus on that before the code.

    If you can't find anything wrong with the clocks you could try to use a mega wizards ROM instead.

    Best Regards,

    Ola Bångdahl
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    --- Quote Start ---

    i'm using quartus II 7.1

    --- Quote End ---

    Hi zadok,

    I tried your code (which you posted ) with QuartusII 8.0 and I got not warning regarding clock transitions. Could post your schematic ?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Hapyang, your clock is probably getting messed up as you have the enable and clock the wrong way round. Try: 

    architecture one of load_counter is
begin
process(clk)
variable temp:std_logic_vector(11 downto 0):="101100110110";
constant a1:std_logic_vector(11 downto 0):="010011001110";
begin
if clk'event and clk='1' then
     if en='1' then
          if temp>a1 then
            temp:=temp-1;
        elsif temp=a1 then
            temp:="101100110110";
        end if;
    end if;
end if;
data_out<=temp;
end process;
end one;