Counter between a data range(VHDL)

It works for me in Modelsim. I would guess that the clock is the problem

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Warning: No clock transition on "db2_rom4:inst30|r_data[1]" register due to stuck clock or clock enable

Warning: Reduced register "db2_rom4:inst30|r_data[1]" with stuck clock port to stuck value GND

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To me this warning says that quartus knows that there isn't a clock signal going into the block. The reason could be that there is an enable signal that is always held to zero or that you've connected the wrong clock signal to the block or something else of that kind. I would focus on that before the code.

If you can't find anything wrong with the clocks you could try to use a mega wizards ROM instead.

Best Regards,

Ola Bångdahl