Counter between a data range(VHDL)

i sorted that out by adding a counter to my statements but i got 700 warnings of the kind below when i compiled my schematic.

Warning: No clock transition on "db2_rom4:inst30|r_data[1]" register due to stuck clock or clock enable

Warning: Reduced register "db2_rom4:inst30|r_data[1]" with stuck clock port to stuck value GND

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most of the code in my blocks looks like this

entity db2_rom1 is

port(r_clk : in std_logic;--clock input at the user data frequency

r_data : out std_logic_vector (9 downto 0)--wavelet data vector representing a portion of the wavelet

);

end db2_rom1;

architecture daze of db2_rom1 is

type mem is array (0 TO 9) of std_logic_vector (9 downto 0);

constant rom : mem :=(

0 => "0000000100",

1 => "0000000111",

2 => "1111101011",

3 => "0000011100",

4 => "1110110100",

5 => "1111101011",

6 => "0011000011",

7 => "1110110100",

8 => "1110011000",

9 => "0000111011"

);

begin

process(r_clk)

variable count : integer :=0;--defining a counter

begin

if rising_edge(r_clk) then

r_data<=rom(count);

count:=count+1;

if count=10 then --check whether the ROM addresses have been exceeded

count:=0;

end if;

end if;

end process;

end daze;