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Altera_Forum
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18 years ago

Counter between a data range(VHDL)

Hi, everyone. This is the Counter I design, lines below: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity load_counter is port( clk:in std_logic; ...
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Altera_Forum
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17 years ago

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i'm using quartus II 7.1

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Hi zadok,

I tried your code (which you posted ) with QuartusII 8.0 and I got not warning regarding clock transitions. Could post your schematic ?