Counter between a data range(VHDL)

I have solved the problerm.

The vhdl lines should be these.

architecture one of load_counter is

begin

process(clk,en)

variable temp:std_logic_vector(11 downto 0):="101100110110";

constant a1:std_logic_vector(11 downto 0):="010011001110";

begin

if en='1' then

if clk'event and clk='1' then

if temp>a1 then

temp:=temp-1;

elsif temp=a1 then

temp:="101100110110";

end if;

end if;

end if;

data_out<=temp;

end process;

end one;