Control SRAM On DE2-115

Question

Hi, I am trying to read and write a buffer on an FPGA, and I want to use SRAM to read and write this buffer. However, I have tried two different methods, but I still couldn't get the SRAM to correctly read (or write) the buffer data.

The first method is using a simple arbitration module written in Verilog. The code is in attachment.

Regarding the inout connections, I wrote them according to the example in the SD Card Music Player ip\TERASIC_SRAM\TERASIC_SRAM.v. I also tried writing them in reverse:

assign sram_dq = sram_we_reg? render_dq : 16'hz;

However, the result is still incorrect.

The second method is using the IP core SRAM Controller, screenshots are in the attachments.

I also used Signal Tap Logic Analyzer to observe the data after downloading it to the FPGA, and the screenshots are also in the attachments(readdata[15..0] line).

The problem now is, regardless of the method used, how can I correctly read and write the buffer in the SRAM? Of course, if you can correct the problems in the code, that would be even better. Thank you!

Software: Quartus Prime 20.1 Lite Edition
FPGA: DE2-115

adzimzm_altera · Answer

Hello,May I know which design that you're used to do the testing?Is it you own design or Intel design example?Do you check if the design is passing timing analysis?Is the pin location has been assigned correctly based on the board?Regards,Adzim

bbbbo15 · Answer

Hi Adzim,Is it you own design or Intel design example?It's my own design.Do you check if the design is passing timing analysis?It says "Quartus Prime Timing Analyzer was successful. 0 errors, 24 warnings".In compilation report, Timing Analyzer/ Unconstrained Paths/Summary, and ../Clock Status Summary is in red color. sorry if i misunderstood it and Time Analyzer, i haven't use Time Analyzer yet.Is the pin location has been assigned correctly based on the board?yes, all pins are assigned correctly in Pin PlannerThank you.