Constraining problems to read external data with an Altera Cyclone V GT FPGA

Dear all,

I am currently working on an VHDL Code and timing constraints, but I have some issues to read serial data from an ADC correctly on a FPGA board.

Short version:

My data pins are DA and DB, which are source synchronous edge aligned to DCO clock from the ADC. The data on DA and DB are updated by every edge of it clock source, but I can not obtain them correctly, due to wrong or incomplete timing constraints. I use set_input_delay function to delay the data to DCO to gather them safely, but this does not work properly and I do not know how to fix it. I wrote my SDC file on my own, based on a SDC file of a demoboard which uses the same ADC, and I also tried the TimeQuest Timing Analyzer.

Long version + system description:

My setup is an Altera FPGA board Cyclone V GT, the ADC LTC2385-18bit on an PCB and I use the HSMC connector.

The FPGA board generates a 5MHz LVDS signal to the CNV pin of the ADC, which starts the conversion cycle. The ADC has two LVDS output pins DA and DB and can operate serially on onelane mode (only DA pin is used, DB is not used) or in twolane mode (DA pin and DB pin are used). After minimum 104 ns data is ready to be shifted out by applying a burst of 9 clock pulses on onelane mode or 5 clock pulses on twolane mode to the CLK input. The CLK has a frequency of 125 MHz and is generated from a PLL, CLK is controlled with an AND-Gate and a self-written enable function.

Data on DA and DB are updated by every edge of CLK and are synchronous and edge aligned to DCO, an echoed version of CLK, which can be used to latch DA and DB in the FPGA. It can also generate a testpattern and I try to read it correctly, at onelane mode it is 10 1000 0001 1111 1100 and at twolane mode it is 11 0011 0000 1111 1100.

My input signals (CNV and CLK) work properly and I can verify all output signals of the ADC with an oscilloscope. My VHDL code to read the data on every edge of DCO is correct and is independent from all other signals and functions. I used the receive code from an demoboard, which uses the same ADC, and changed it from Verilog to VHDL.

The Problem now is to obtain the data correctly. I used the SDC code from the Demoboard and changed it, but this did not work. Then I tried to generate my own SDC file with the TimeQuest Timing Analyzer Quick Start Tutorial. This works better but my data is still not correct, and it generates many constrains, because of other components I need but which are unknown to me. Now I have deleted these other constrains to look at their effect, but I receive the same data.

My best results, after lots of changing, are one wrong bit on onelane mode (10 1000 0000 1111 1100 instead of 10 1000 0001 1111 1100) and three wrong bits on twolane mode (11 0011 0100 0011 1100 instead of 11 0011 0000 1111 1100), but these results are inconsistent.

Thanks in Advance.

This is my current SDC file:

set_time_format -unit ns -decimal_places 3# ####################################  for 100MHz ref clock
set period_refclk    10# ####################################  for 125MHz AVMM clock
set period_mgmt  8# ###################################
create_clock -name {refclk}  -period $period_refclk   
create_clock -name {mgmt_clk}    -period $period_mgmt # ####################################  the measured time HSMC CLK port to HSMC DCO port is 1.8ns# ###################################
create_generated_clock -name DCO -source  -edges {1 2 3} -edge_shift {2 2 2} # ####################################  Input delay# ###################################
set_input_delay -clock {DCO} -clock_fall -rise -min 0.8 
set_input_delay -clock {DCO} -clock_fall -rise -max 1.2 
set_input_delay -clock {DCO} -clock_fall -fall -min 0.8 
set_input_delay -clock {DCO} -clock_fall -fall -max 1.2 
 
set_input_delay -clock {DCO} -clock_fall -rise -min 0.8 
set_input_delay -clock {DCO} -clock_fall -rise -max 1.2 
set_input_delay -clock {DCO} -clock_fall -fall -min 0.8 
set_input_delay -clock {DCO} -clock_fall -fall -max 1.2 # ####################################  Set_false_path# ###################################
set_false_path -from  -to 
set_false_path -from  -to .gpll~PLL_OUTPUT_COUNTER|divclk}]
 
derive_pll_clocks
derive_clock_uncertainty