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Altera_Forum
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8 years ago

Constraining problems to read external data with an Altera Cyclone V GT FPGA

Dear all, I am currently working on an VHDL Code and timing constraints, but I have some issues to read serial data from an ADC correctly on a FPGA board. Short version: My data pins are...
Altera_Forum's avatar
Altera_Forum
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8 years ago

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Hi,

I just found this thread and wondered if you solved the problem of aligning the DCO clock to the center of DA,DB ?

I have the same issue now and am considering a pll solution based on 1 pll o/p driving the data clocking and a second o/p clocking the DDR.

Cheers, S.

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Actually, it looks like the answer is here http://www.alterawiki.com/uploads/e/ea/source_synchronous_timing.pdf on Page 47.