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Honored Contributor
Honored ContributorConstraining problems to read external data with an Altera Cyclone V GT FPGA
Dear all, I am currently working on an VHDL Code and timing constraints, but I have some issues to read serial data from an ADC correctly on a FPGA board. Short version: My data pins are...
Altera_ForumHonored Contributor
Honored ContributorHi,
I just found this thread and wondered if you solved the problem of aligning the DCO clock to the center of DA,DB ? I have the same issue now and am considering a pll solution based on 1 pll o/p driving the data clocking and a second o/p clocking the DDR. Cheers, S.
