Honored Contributor
Honored ContributorHi,
--- Quote Start --- Is it correct that the set_input_delay function delays the target signal to the source signal with the delay time? --- Quote End --- NO, with set_input_delay you are describing external delays on input data. Your assumption that you are delaying signal with set_input_delay is wrong. --- Quote Start --- The data on DA and DB are updated by every edge --- Quote End --- You are saying that data is updated by every edge but in set_input_delay you only using -clock_fall option. --- Quote Start --- The CLK has a frequency of 125 MHz and is generated from a PLL, CLK is controlled with an AND-Gate and a self-written enable function. --- Quote End --- Do you use some logic gates in your clk path?
