Constraining problems to read external data with an Altera Cyclone V GT FPGA

Hi,

Thanks for your reply.

Ok, then I had misinterpreted the set_input_delay function. How can I delay my DCO by 1 ns? I cannot use a PLL to phase shift my DCO, because it is not continuously.

I had used an AND-gate with a clock and a clock enable signal to get 9 clock pulses, but I replaced the AND-gate with an ALTDDIO_OUT IP Core, which does the same but my enable code is much shorter.

I found the file Timing Analysis of Internally Generated Clocks in Timequest v2.0 in this Thread https://www.alteraforum.com/forum/showthread.php?t=2250 and tried the instructions on pp.13-16, but I cannot use -master_clock because Quartus cannot compile my System and the error message says 'use a larger device'. Without the -master_clock I am able to do a compilation but I still cannot read my Data correctly.