Constraining problems to read external data with an Altera Cyclone V GT FPGA

Dear all,

some time has passed now but nobody has answered my questions so far. Are there any problems of understanding concerning my formulations or is it simply the problem itself?

I do have some more questions concerning my problem as well:

Is it correct that the set_input_delay function delays the target signal to the source signal with the delay time?

And add a later set_input_delay function with -add_delay additional delay time to my existing delay function?

I am trying to delay the edges of my source signal to a stable level of my data signal.

I would be very happy, if somebody could please answer my questions, I am working on my Bachelor thesis and these timing constraints are posing a huge problem to my project.

Thanks in advance,

altera_hawx