Altera_Forum
Honored Contributor
Honored ContributorConstrained clock appears as unconstrained input
Hello,
I've spent a considerable amount of time several months ago to look into timing constraint issues, but had never understood how it works ... all this staff, despite several manuals I looked through. Then I abandoned it in favour of other things. Recently I returned to that work, and once more face these issues. So here is my constraint file - it was generated by Terasic System Builder and then I added some additional instructions, in particular, create_clock and create_generated_clock. Timing Analysis reports 2 violations: one unconstrained input port and on unconstrained output port. CLOCK_50 No input delay, min/max delays, false-path exceptions, or max skew assignments found. This port has clock assignment. DRAM_CLK No output delay, min/max delays, false-path exceptions, or max skew assignments found. This port has clock assignment. But input port is part of create_clock instruction, so must be considered as constrained, and output port is part of create_generated_clock instruction, so also must be considered as constrained (if my comprehension is correct). Where I've been mistaken ? Thanks in advance.#**************************************************************# This .sdc file is created by Terasic Tool.# Users are recommended to modify this file to match users logic.# **************************************************************
# **************************************************************# Create Clock# **************************************************************
create_clock -period 20.0 -name clk CLOCK_50
create_clock -period 20.0 -name clk_dram# create_clock -period "100 MHz" -name clk_dram
# for enhancing USB BlasterII to be reliable, 25MHz
create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck}
set_input_delay -clock altera_reserved_tck -clock_fall 3
set_input_delay -clock altera_reserved_tck -clock_fall 3
set_output_delay -clock altera_reserved_tck 3
# **************************************************************# Create Generated Clock# **************************************************************
create_generated_clock -name clk_sdram_ext -source # derive_pll_clocks
# **************************************************************# Set Clock Latency# *************************************************************
# **************************************************************# Set Clock Uncertainty# **************************************************************
derive_clock_uncertainty
# **************************************************************# Set Input Delay# **************************************************************# Board Delay (Data) + Propagation Delay - Board Delay (Clock)
set_input_delay -max -clock clk_dram -0.048
set_input_delay -min -clock clk_dram -0.057
# **************************************************************# Set Output Delay# **************************************************************# max : Board Delay (Data) - Board Delay (Clock) + tsu (External Device)# min : Board Delay (Data) - Board Delay (Clock) - th (External Device)
set_output_delay -max -clock clk_dram 1.452
set_output_delay -min -clock clk_dram -0.857
set_output_delay -max -clock clk_dram 1.531
set_output_delay -min -clock clk_dram -0.805
set_output_delay -max -clock clk_dram 1.533
set_output_delay -min -clock clk_dram -0.805
set_output_delay -max -clock clk_dram 1.510
set_output_delay -min -clock clk_dram -0.800
set_output_delay -max -clock clk_dram 1.520
set_output_delay -min -clock clk_dram -0.780
set_output_delay -max -clock clk_dram 1.5000
set_output_delay -min -clock clk_dram -0.800
set_output_delay -max -clock clk_dram 1.545
set_output_delay -min -clock clk_dram -0.755
set_output_delay -max -clock clk_dram 1.496
set_output_delay -min -clock clk_dram -0.804
set_output_delay -max -clock clk_dram 1.508
set_output_delay -min -clock clk_dram -0.792
# **************************************************************# Set Clock Groups# **************************************************************
# **************************************************************# Set False Path# **************************************************************
set_false_path -from
set_false_path -from
set_false_path -from * -to
set_false_path -from * -to
