Constrained clock appears as unconstrained input

I'm totally desperate

I still cannot resolve this issue with unconstrained path, related to output clock.

According to different documents, I've examined until now, the a port, that is target in create_generated_clock constraint is considered as constrained.

... at least in multiple examples if output port serves as target in create_generated_clock constraint, there is no set_output_delay constraint for this port.

Indeed, in other design that I've created some time ago and that is very similar to the actual one (I'm working on now), the identical output port isn't signaled as unconstrained.

I'v reduced the dissimilarities of these two designs to a minimum ... I've even instantiated the qsys module from "good" design into the "bad" one.

Does't help !!!

The output port is still signaled as unconstrained.

What should I check in my design to track down this mysterious issue.

Thanks in advance.