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Without seeing the constraints or the design, there's no way for me to know why they are different.
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"Good" design constraints:
create_clock -name clk -period 20 create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck}
derive_pll_clocks
derive_clock_uncertainty
set_input_delay -clock altera_reserved_tck -clock_fall 3
set_input_delay -clock altera_reserved_tck -clock_fall 3
set_output_delay -clock altera_reserved_tck 3
create_generated_clock -name clk_ext_sdram -source .gpll~PLL_OUTPUT_COUNTER|divclk}]
# Constraint SDRAM DATA for input
set_input_delay -clock clk_ext_sdram -max 6.4 ]
set_input_delay -clock clk_ext_sdram -min 1.0 ]
# Constraint SDRAM DATA for output
set_output_delay -clock clk_ext_sdram -max 1.5
set_output_delay -clock clk_ext_sdram -min -0.8
# set_multicycle_path -setup -to }] 2# set_multicycle_path -hold -to }] 1
set_false_path -from
set_false_path -from
set_false_path -from * -to
set_false_path -from * -to
"Bad" design constraints:
#**************************************************************# This .sdc file is created by Terasic Tool.# Users are recommended to modify this file to match users logic.# **************************************************************
# **************************************************************# Create Clock# **************************************************************
create_clock -period 20.0 -name clk CLOCK_50
# for enhancing USB BlasterII to be reliable, 25MHz
create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck}
derive_pll_clocks
derive_clock_uncertainty
set_input_delay -clock altera_reserved_tck -clock_fall 3
set_input_delay -clock altera_reserved_tck -clock_fall 3
set_output_delay -clock altera_reserved_tck 3
# **************************************************************# Create Generated Clock# **************************************************************
create_generated_clock -name clk_sdram_ext -source .gpll~PLL_OUTPUT_COUNTER|divclk}]
create_generated_clock -name clk_data -source .gpll~PLL_OUTPUT_COUNTER|divclk}] |clk}]
# **************************************************************# Set Input Delay# **************************************************************# Board Delay (Data) + Propagation Delay - Board Delay (Clock)
set_input_delay -clock clk_sdram_ext -max -0.048
set_input_delay -clock clk_sdram_ext -min -0.057
# **************************************************************# Set Output Delay# **************************************************************# max : Board Delay (Data) - Board Delay (Clock) + tsu (External Device)# min : Board Delay (Data) - Board Delay (Clock) - th (External Device)
set_output_delay -clock clk_sdram_ext -max 1.452
set_output_delay -clock clk_sdram_ext -min -0.857
set_output_delay -clock clk_sdram_ext -max 1.531
set_output_delay -clock clk_sdram_ext -min -0.805
set_output_delay -clock clk_sdram_ext -max 1.533
set_output_delay -clock clk_sdram_ext -min -0.805
set_output_delay -clock clk_sdram_ext -max 1.510
set_output_delay -clock clk_sdram_ext -min -0.800
set_output_delay -clock clk_sdram_ext -max 1.520
set_output_delay -clock clk_sdram_ext -min -0.780
set_output_delay -clock clk_sdram_ext -max 1.5000
set_output_delay -clock clk_sdram_ext -min -0.800
set_output_delay -clock clk_sdram_ext -max 1.545
set_output_delay -clock clk_sdram_ext -min -0.755
set_output_delay -clock clk_sdram_ext -max 1.496
set_output_delay -clock clk_sdram_ext -min -0.804
set_output_delay -clock clk_sdram_ext -max 1.508
set_output_delay -clock clk_sdram_ext -min -0.792
# **************************************************************# Set False Path# **************************************************************
set_false_path -from
set_false_path -from
set_false_path -from * -to
set_false_path -from * -to
"Good" design top module
module nios_led2_top (input clk, input sw,
input key,
output led_l, led_h,
output hex3, hex2 , hex1, hex0,
output sdram_addr,
inout sdram_dq,
output sdram_bank,
output sdram_cas_n, sdram_ras_n, sdram_cke, sdram_cs_n, sdram_clk,
output sdram_dqmh, sdram_dqml, sdram_we_n);
wire sseg;
assign hex3 = sseg;
assign hex2 = sseg;
assign hex1 = sseg;
assign hex0 = sseg;
nios_led2_sdram u0 (
.btn_export (key),
.clk_clk (clk),
.led_l_export (led_l),
.led_h_export (led_h),
.reset_reset_n (1'b1),
.sdram_wire_addr (sdram_addr),
.sdram_wire_ba (sdram_bank),
.sdram_wire_cas_n (sdram_cas_n),
.sdram_wire_cke (sdram_cke),
.sdram_wire_cs_n (sdram_cs_n),
.sdram_wire_dq (sdram_dq),
.sdram_wire_dqm ({sdram_dqmh, sdram_dqml}),
.sdram_wire_ras_n (sdram_ras_n),
.sdram_wire_we_n (sdram_we_n),
.sseg_export (sseg),
.switch_export (sw),
.clk_sdram_clk (sdram_clk)
);
endmodule
"Bad" design top module:
//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
module ch_11(
//////////// CLOCK //////////
input CLOCK_50,
//////////// SDRAM //////////
output DRAM_ADDR,
output DRAM_BA,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_CLK,
output DRAM_CS_N,
inout DRAM_DQ,
output DRAM_LDQM,
output DRAM_RAS_N,
output DRAM_UDQM,
output DRAM_WE_N,
//////////// SEG7 //////////
output HEX0,
output HEX1,
output HEX2,
output HEX3,
//////////// KEY //////////
input KEY,
//////////// LED //////////
output LEDR,
//////////// SW //////////
input SW
);
//=======================================================
// REG/WIRE declarations
//=======================================================
//=======================================================
// Structural coding
//=======================================================
// ch_11_nios u0 (
// .clk_clk (CLOCK_50), // clk.clk
// .reset_reset_n (1'b1), // reset.reset_n
// .switch_export (SW), // switch.export
// .btn_export (KEY), // btn.export
// .sseg_export ({{1'b0,HEX3},{1'b0,HEX2},{1'b0,HEX1},{1'b0,HEX0}}), // sseg.export
// .sdram_addr (DRAM_ADDR), // sdram.addr
// .sdram_ba (DRAM_BA), // .ba
// .sdram_cas_n (DRAM_CAS_N), // .cas_n
// .sdram_cke (DRAM_CKE), // .cke
// .sdram_cs_n (DRAM_CS_N), // .cs_n
// .sdram_dq (DRAM_DQ), // .dq
// .sdram_dqm ({DRAM_UDQM, DRAM_LDQM}), // .dqm
// .sdram_ras_n (DRAM_RAS_N), // .ras_n
// .sdram_we_n (DRAM_WE_N), // .we_n
// .led_export (LEDR), // led.export
// .sdram_clk_clk (DRAM_CLK) // sdram_clk.clk
// );
nios_led2_sdram u0 (
.btn_export (KEY),
.clk_clk (CLOCK_50),
.led_l_export (LEDR),
.led_h_export (LEDR),
.reset_reset_n (1'b1),
.sdram_wire_addr (DRAM_ADDR),
.sdram_wire_ba (DRAM_BA),
.sdram_wire_cas_n (DRAM_CAS_N),
.sdram_wire_cke (DRAM_CKE),
.sdram_wire_cs_n (DRAM_CS_N),
.sdram_wire_dq (DRAM_DQ),
.sdram_wire_dqm ({DRAM_UDQM, DRAM_LDQM}),
.sdram_wire_ras_n (DRAM_RAS_N),
.sdram_wire_we_n (DRAM_WE_N),
.sseg_export ({{1'b0,HEX3},{1'b0,HEX2},{1'b0,HEX1},{1'b0,HEX0}}),
.switch_export (SW),
.clk_sdram_clk (DRAM_CLK)
);
endmodule
Here is unconstrained output in "Bad" module:
DRAM_CLK No output delay, min/max delays, false-path exceptions, or max skew assignments found. This port has clock assignment.
Honored Contributor
