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Honored ContributorConstrained clock appears as unconstrained input
Hello, I've spent a considerable amount of time several months ago to look into timing constraint issues, but had never understood how it works ... all this staff, despite several manuals I loo...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- In the "good" constraints, you've created a set_output_delay targeted to sdram*. Thus, this output delay constraint is covering the data output timing of this output clock, which as I mentioned, should not be constrained because you want it analyzed as a clock path, not a data path. Thus, you don't get the unconstrained path. In the "bad" constraints, you're not doing this, so DRAM_CLK appears unconstrained because it's still considered a data path. --- Quote End --- Indeed, it's the case. Thanks a lot !
